SPD spec on Wiki

http://en.wikipedia.org/wiki/Serial_presence_detect#SDR_SDRAM

Check Offset 5: memory type (SDR SDRAM/ DDR SDRAM/ DDR2 SDRAM/ DDR3 SDRAM)

Check # of banks

Check module bank density (512Mb, 1G so on)

DIMM size = module bank density x # of banks

Where is Driver in NetBsd code base

SW-NetBSD/usr/src/sys/arch/evbppc/moduleName/componentKernelDrivers.c

i.e. i2c.c asicA.c fpgaB.c

• contain open/close/ioctl calls and HW init function.
• This level calls real low driver.
• This level does not implements semaphore.
• Device address/offset or register address passed thru via caddr_t structure. Format user definable?

Volatile identifier in C

• Used for variables
• To avoid compiler optimization
• Used for memory mapped IO

Compiler Optimization (Example)

static int val;

void func1() {

val = 0;

while (val != 0xff) // optimize as while(1)

;

}

void func2() {

val = 0;

while (*(volatile int *) &val != 0xff) // no optimization applied

;

}

RTOS

Real time OS implements mechanism to support low latency to requests (mainly from HW) Used in critical system.

• Multi-tasking
• Preemtion (time sharing & context switching)
• Interrupt handler == ISR (interrupt service routine) <--> Polling
• Mutual exclusion (semaphore)

Dead lock/ Example: circular waiting

A <- B <- C and then C <- A

ISR

• Callback called when interrupt occur
• An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table that contains the memory addresses of interrupt handlers.
• Cpu registers define what kind of interrupt (I2c, Packet Rx, HW so on)
• SW / HW interrupt

(From Wiki) A hardware interrupt causes the processor to save its state of execution and begin execution of an interrupt handler.

Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt.

JEDEC Industrial standard

For Memory SPD

http://www.jedec.org/category/technology-focus-area/memory-configurations-jesd21-c

I2c bus

• Serial bus.
• Originally proposed by Philips
• 400KHz - Slow
• 8 or 16 bits.

• I2c protocol

It uses only 2 signals (wires) Clock & Data.

The following protocol is implemented between master (CPU) and Slave devices.

START

C: H

D: Fall

STOP

C: H

D: Rise

ACK

C: H

D[9] = H or L

Send Address + D[0]command(Read)

Get ACK

Get Data

Send Address + D[0]command(Write)

Get ACK

Send Data

Untagged Vlan config

• Vlan is a layer 2 protocol to set up logical sub network.
• single subnetwork => untagged
• multiple subnetwork ==> tagged (ID in Ethernet frame) == IEEE802.1Q

• (Untagged) Vlan config for FIG 1 Across PP (linecard 5)

FIG1 Across PP

#sh vlan

Codes: * - Default VLAN, G - GVRP VLANs

Q: U - Untagged, T - Tagged

x - Dot1x untagged, X - Dot1x tagged

G - GVRP tagged, M - Vlan-stack

NUM Status Description Q Ports

* 1 Inactive

2 Active U Te 5/0,3

3 Active U Te 5/1-2

#

· Vlan config for FIG 2 Same PP (linecard 5)

FIG2 Same PP

#conf

(conf)#int vlan 20

(conf-if-vl-20)#untag ten 5/0

(conf-if-vl-20)#untag ten 5/1

(conf-if-vl-20)#exit

(conf)#int vlan 21

(conf-if-vl-21)#untag ten 5/2

(conf-if-vl-21)#untag ten 5/3

(conf)#exit

#sh vl

Codes: * - Default VLAN, G - GVRP VLANs, P - Primary, C - Community, I - Isolated

Q: U - Untagged, T - Tagged

x - Dot1x untagged, X - Dot1x tagged

G - GVRP tagged, M - Vlan-stack

NUM Status Description Q Ports

* 1 Inactive

20 Active U Te 5/0-1

21 Active U Te 5/2-3

Force10#

· MTU should be jumbo frame

con

int rang te 5/0 - 3

mtu 9252

exit

· Also check line rate

#sh int tengiga 5 | grep line-rate|TenGi